ASE Targets Q1 2027 Initial Production for AMD Venice Panel-Level Packaging

25 Venice Interposers on a Square Panel

ASE Technology Holding put panel-level packaging hardware built for Advanced Micro Devices' next-generation Venice server processor on display at the Open Compute Project summit, with initial production targeted for the first quarter of 2027. The semiconductor research firm SemiAnalysis described the demonstration in a post published on X on October 28, adding that early output would probably run at limited scale at ASE's Kaohsiung site. Panel-level packaging replaces the round wafer as the working surface for advanced packages: square chips and interposers arranged on a square panel waste less material at the edges, so each batch carries more units and unit costs fall with scale.

According to SemiAnalysis, ASE and its subsidiary SPIL have worked with AMD to implement a second generation of fan-out embedded bridge (FOEB) technology on Venice. The interposer, the base layer that connects multiple dies inside a single package, spans 2.7 reticle field sizes in this design. One 310 by 310 millimeter panel holds 25 Venice interposers once edge losses are counted, against 22 on a conventional 300 millimeter round carrier, roughly 14% more units per batch. SemiAnalysis treats that gain as a starting point rather than a cost breakthrough. The margin widens as interposers grow: a 9.5 reticle field design yields 9 units per panel against 4 per wafer, about 2.25 times as many, though the step depends on equipment for larger panels and reticle fields maturing first. Venice is AMD's sixth-generation EPYC server processor. AMD said in May that production had started ramping on Taiwan Semiconductor Manufacturing Company's 2-nanometer process, while ASE's own guidance from May pointed to mass production in the first half of 2027; the research note narrows the start to the first quarter.

PTI Cleared for $400 Million Singapore Plant

Taiwan's Investment Commission under the Ministry of Economic Affairs approved on October 28 an investment of US$400 million, about NT$12.8 billion, by Powertech Technology (PTI, 6239) to set up XCIP TECHNOLOGIES PTE. LTD. in Singapore, a company covering panel-level advanced packaging, assembly and final testing services. The clearance satisfies the regulatory condition attached when PTI's board approved the joint venture with Broadcom on July 16. The venture focuses on fine-line redistribution layer technology for advanced packaging substrates, the layer that re-routes chip connections onto the package board.

Under the agreement, Broadcom is expected to take a majority stake and lead the facility, while PTI holds no more than half and runs operations and mass production. The plant could break ground by the end of 2026 at the earliest and reach production in 2028, with demand from co-packaged optics, the approach that places optical engines beside switching silicon for high-speed data links, as its target market. Neither side has disclosed the final equity split or the total venture amount. PTI built its business on packaging and testing DRAM and NAND flash memory, and has put panel-level work, including fan-out panel-level packaging (FOPLP) and heterogeneous integration, among its strategic priorities as it tries to reduce dependence on memory market cycles. The Singapore project moves that shift into capital: a working production line would extend the company from memory services toward supply chains for custom AI accelerators and high-end logic chips, segments where Broadcom has been expanding its ASIC and switching businesses for cloud customers. The schedule also fits the wider build-out: TSMC has said its CoPoS panel-level platform is due to complete development by 2027 and launch in 2028, led by its assembly and test partners, with glass substrate validation underway alongside Ibiden and Innolux.

The two announcements read as one build-out rather than separate bets. ASE's Q1 2027 start and PTI's 2028 production both land inside the window TSMC has set for its own panel-level transition, which points to 2027 and 2028 as the period when this capacity arrives across the supply chain at once. The economics SemiAnalysis lays out also explain the order of events: the 14% density gain on Venice is a baseline, and the payoff comes only with larger interposers and mature equipment. For PTI, the clearance turns a tester shaped by memory cycles into a prospective supplier for AI ASIC packaging, where demand follows Broadcom's cloud customers rather than DRAM prices.